iNEMI Announces Wafer/Panel Level Fine Pitch Substrate Inspection/Metrology Project

The fine pitch substrate features of advanced packaging technologies such as SiP, 2.5D, etc., can directly impact yield and performance of the package. iNEMI’s Wafer/Panel Level Fine Pitch Substrate Inspection/Metrology project has been organized to address the need to identify and characterize the capabilities of inspection technologies that can enable faster inspection and process development and, ultimately, higher yield in high-volume production.

This webinar will share the findings and recommendations from Phase 2 of the project, which studied the available measurement capabilities for fine line (<10um) and space (<10um) designs and defect patterns on glass-based and silicon wafer-based test vehicles (TVs). Phase 2 was led by Feng Xue (IBM), Charles Woychik (i3 Electronics) and Charles Reynolds (IBM). For additional project information.

In addition, the webinar will outline the plans for the next phase of the project, which will focus on fabrication and inspection of organic substrates, using the TV designs from Phase 2. The team, led by Feng Xue (IBM), Joe Zou (Intel) and Charles Reynolds (IBM), plans to evaluate and quantify the limitations of automatic optical inspection (AOI) for fine pitch and defect patterns on organic substrates, and compare them to other relevant inspection methodologies. For additional project information.

The Phase 2 end-of-project webinar is being combined with the Phase 3 call-for-participation webinar. Two sessions are scheduled and are open to members and non-members. Participants must register in advance — please click on the links below to register. For additional information, contact Masahiro Tsuriya (m.tsuriya@inemi.org)

March 5

10:00 a.m. JST (Japan)

8:00 p.m. EST (USA) on March 4

5:00 p.m. PST (USA) on March 4

Register for this webinar

March 5

8:00 a.m. EST (USA),

2:00 p.m. CET (Europe)

10:00 p.m. JST (Japan)

Register for this webinar