Self-driving cars pushing boundaries of IC testing: Nilanjan Mukherjee, Mentor
Nilanjan Mukherjee, Engineering director, Tessent, Mentor A Siemens Business, presented the opening keynote on day two of the ITC 2018 in Bangalore this week. His presentation was on self-driving cars and how they are pushing the boundaries of IC testing.
Automotive ICs will grow from 7.4 percent in 2017 to 9.3 percent by 2021. New entrants are attracted by new revenue opportunities. Leading auto makers are planning to launch self-driving cars, such as Tesla, GM, Hyundai, Renault-Nissan, Toyota, Volvo, etc., as per Boston Consulting Group. According to McKinsey & Co., 57 percent of customers globally, trust self-driving cars.
Increasing detection capabilities require higher compute performance. Higher compute requirements are accelerating process node requirements. For the next decade, the number of gates will double every two years. There will be 2x more compression every two years, just to maintain the test cost. There is a big increase in transistor processing and trends will continue with future 5nm/3nm nodes. Further scaling requires density increase in addition to pitch scaling.
Test requirements mean semiconductor devices must remain defect free. They should also ensure that any new defects are quickly detected throughout the device operational lifecycle. Low defective parts per billion are critical: the implications of defective parts in automotive apps are more severe than in consumer apps. Defect coverage should cover all circuitry.
More defects and lower DPPB require better coverage. There are complete defect excitation considerations. The defects are prioritized by physical likelihood.
Automotive grade ATPG provides a complete set of critical area based fault models for manufacturing tests. Cell-aware test benefits are well documented. Additional user–defined fault models (UDFM) are targeting inter-cell defects and interconnect bridges and open defects. We have to find ways to reduce test time for analog parts. Typically low coverage is 70-90 percent for analog parts. Fault simulation allows one to determine portions not being tested. Eliminate manual FMEDA metric estimates that are required for ISO-26262. The fault simulator can report the metrics automatically, eliminating untolerated faults and achieve higher ASIL rating.
There are multiple modes of in-system testing. Key on tests have very little time budget. Limited functions are tested. Key off tests see comprehensive testing. The budget is 10x times that of key on tests. Online tests are challenging. They are periodic and incremental.
Mission-mode controller is the in-system test controller. It automates communication between the test instruments and the service processor.
New VersaPointt test point technology gives 2-4 percent SAF coverage vs. LBIST test points. That’s 2X-3X reduction in test time at 90 percent coverage. It also reduces deterministic ATPG pattern counts by 2-4X.
VersaPoint test points with observation during shift helps in fast in-system logic monitoring. This helps on an average to reduce the test times by 3-4X.
Requirements for future in-system test solutions:
* Able to apply any type of test
* Able to add, modifym update the in-system tests during the entire lifecycle of an IC
* Minimal system memory and incremental data.
Programmable deterministic BIST for FuSa include two levels of highly compressed patterns. This reduces the memory required to store the patterns on the chip.
In the non-destructive memory BIST, there are traditional memory BIST constraints. Memory is tested in small bursts of activity by making sure that the original contents of the memory is restored after test.
Austemper acquisition by Siemens brings solutions across all areas. It is a completely functional safety solution. There is safety analysis, so you can design for safety. It also has safety verification, and multi-domain fault injection providing evidence to achieve ASIL compliance.
Automotive ICs have redefined the standard for quality of manufacturing.
