International Wafer-Level Packaging Conference (IWLPC) Program Announced and Registration Now Open  

Minneapolis, MN –  The Surface Mount Technology Association (SMTA) and Chip Scale Review are pleased to announce the program for the 16th annual International Wafer-Level Packaging Conference (IWLPC). The conference will be held October 22-24, 2019 at the DoubleTree by Hilton Hotel in San Jose, California.

The technical sessions on Tuesday and Wednesday are organized into three tracks: Wafer-Level Packaging, 3D Packaging, and Advanced Manufacturing and Test. The Wafer-Level Packaging (WLP) track features sessions on materials, reliability, metrology, processing, and new technology, such as Fan-Out WLP. The 3D Packaging track features sessions on design, test, characterization, wafer bonding, chip stacking, and processing for fan-out. The Advanced Manufacturing and Test track features sessions on process materials, equipment, inspection, and more.

Packaging technology experts John Lau, Ph.D., Unimicron Technology; John Hunt, ASE (US) Inc.; Gilad Sharon, Ph.D., ANSYS and Jeff Gotro, Ph.D., InnoCentrix, LLC, are scheduled to lead half-day workshops on Thursday, October 24, 2019.

Registration for IWLPC is now available online. Discounted rates are available for conference registration made on or before September 27, 2019. Visit www.iwlpc.com for more information. Contact Jaclyn Sarandrea at +1-952-920-7682 or jaclyn@smta.org with questions.

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