Pradeep caught up with his good friend, Jaswinder Ahuja, Corporate VP & MD of Cadence Design Systems India Pvt Ltd, and asked him about the global semiconductor industry trends for 2019. So, how is the global semicon industry performing this year? How does Cadence see it going in 2019?
Global semicon industry trends
Jaswinder Ahuja said: “The semiconductor industry is doing very well. Estimates say that it has crossed $400 billion in revenue. This growth is being driven by four or five waves that have emerged over the last couple of years. These are:
- Cloud and data center applications are booming, and the top names in this space, including, Amazon and Google are now designing their own chips.
- Automotive is (and has been) going through a transformation over the last few years. ADAS is just the beginning. From infotainment to safety, the whole vehicle is driven on precision electronics.
- Industrial IoT is another wave. By incorporating artificial intelligence (AI) to manufacturing and industrial processes, we are looking at a revolution—what is being called Industry 4.0.
- Mobile and wireless have, of course, driven growth in the last decade to decade-and-a-half, and it doesn’t show any signs of slowing down.
- Consumer and IoT devices can also be considered a wave, although the consumer wave started some time ago. IoT is the game-changer there, with so many billion connected devices being forecasted in the next 5-10 years.
“Thanks to these technology waves, our sense is that the growth will continue into 2019, and probably beyond, especially as AI and ML become more prevalent across applications.”
Global EDA and memory industries
How is the global EDA industry performing this year? How do you see it going next year in 2019?
He said: “Cadence has seen strong results in 2018 so far across product lines. This is thanks to multiple technology waves, especially machine learning, that are driving increased design activity and our System Design Enablement strategy, as well as our continued focus on innovation and launching new products.”
And, what’s the road ahead for memory? Is memory attracting more investment?
He added: “The memory market is being driven by the data-driven economy, and the need to store and process data at the edge and in the cloud. Added to that is the huge demand for smart and connected devices, for which memory is crucial.
“There isn’t any data about investments, but keeping in mind the consolidation that is happening across the industry, it could well be that we may witness some industry M&A activity with memory companies as well. The merger of SanDisk and Western Digital is one such example.”
EUV lithography trends
Has EUV lithography progressed? By when is EUV lithography likely to get mainstream?
Ahuja noted: “As technology advances, both manufacturing and design complexity grow. Designs are being scaled down to meet the ever-increasing demand for more functionality contained in a single chip, creating unique implementation challenges.
“Manufacturing is facing huge challenges in terms of printability, manufacturability, yield ramp-up and variability. Unfortunately, restrictions on power, performance and area (PPA) or turnaround time (TAT) do not scale up along with these factors.
“Foundries have been talking about EUV for years now. However, the power and performance improvements with EUV don’t look very significant at this time. Clearly, there is still some distance to go, before EUV will become mainstream.
“On a related note, in February 2018, Cadence and imec, the world-leading research and innovation hub in nanoelectronics and digital technologies, announced that its extensive, long-standing collaboration had resulted in the industry’s first 3nm test chip tapeout.
“The tapeout project, geared toward advancing 3nm chip design, was completed using EUV and 193 immersion (193i) lithography-oriented design rules, and the Cadence Innovus Implementation System and Genus Synthesis Solution.”
Trends in power and verification
Finally, what is the latest regarding coverage and power across all the aspects of verification?
He said: “Over the past decade, verification complexity and demands on engineering teams have continued to rise rapidly. Applying innovative solution flows, automation tools, and best-in-class verification engines is necessary to overcome the resulting verification gap.
“With regard to verification coverage, the challenge is always to know when you are done (the process of verification signoff). Cadence has a unique methodology and technology for measuring and signing off on the design and verification metrics used during the many milestones typical in any integrated circuit (IC) development, and it is called Metric Driven Verification (MDV).
“While milestones and metrics vary by design type and end-application, the final verification signoff will, at a minimum, contain the criteria and metrics within a flexible, human-readable and user-defined organizational structure. Automated data collection, project tracking, dashboards and in-depth report techniques are mandatory elements to eliminate subjectivity, allowing engineers to spend more time on verification and less time manually collecting and organizing data.
“Power-optimization techniques are creating new complexities in the physical and functional behavior of electronic designs. An integral piece of a functional verification plan, Cadence’s power-aware verification methodology can help verify power optimization without impacting design intent, minimizing late-cycle errors and debugging cycles. After all, simulating without power intent is like simulation with some RTL code black-boxed.
“The methodology brings together power-aware elaboration with formal analysis and simulation. With power-aware elaboration, all of the blocks as well as the power management features in the design are in place, so design verification with power intent is possible. Power intent introduces power/ground nets, voltage levels, power switches, isolation cells, and state retention registers. Any verification technology—simulation, emulation, prototyping, or formal—can be applied on a power-aware elaboration of the design.”